003. CPU 总线到 RAM

让 CPU RAM 地址经由 CpuBus 路由。

第 3 / 356 · tests/chapter_01_cpu/test_003_cpu_bus_to_ram.py

需要更新的文件

emulator/bus/cpu_bus.py

位置

class CpuBus

参考

https://www.nesdev.org/wiki/CPU_memory_map

此步骤存在的原因

CPU 使用 16 位地址空间，而内部 RAM 只有 0x800 个物理字节。地址 $0000-$1FFF 会将同一块 RAM 重复映射四次。

完整示例实现

from dataclasses import dataclass, field

from emulator.memory.ram import RAM


@dataclass
class CpuBus:
    ram: RAM = field(default_factory=RAM)

    def read(self, addr: int) -> int:
        if 0x0000 <= addr <= 0x1FFF:
            return self.ram.read(addr & 0x07FF)

        raise ValueError(f"Unsupported CPU bus read: {addr:04X}")

    def write(self, addr: int, value: int) -> None:
        if 0x0000 <= addr <= 0x1FFF:
            self.ram.write(addr & 0x07FF, value)
            return

        raise ValueError(f"Unsupported CPU bus write: {addr:04X}")

重要不变量

physical_ram_address = cpu_address & 0x07FF

最小示例

向 CPU 地址 $0800 写入 $42 会改变物理 RAM 中偏移 $0000 处的字节，因此读取 $0000、$0800、$1000 或 $1800 都会看到同一份存储。

常见误解

镜像并不会分配四份 RAM 数组。总线把四个 CPU 地址区间都转换到同一个 RAM 设备上。在这一步中，不受支持的地址会引发 ValueError，而 bytearray 本身会拒绝超出无符号 8 位范围的值。

范围之外

程序 ROM 路由
PPU 和手柄寄存器
CPU 执行

运行本课

uv run pytest tests/chapter_01_cpu/test_003_cpu_bus_to_ram.py -v

示例实现

完整示例实现

from dataclasses import dataclass, field

from emulator.memory.ram import RAM


@dataclass
class CpuBus:
    ram: RAM = field(default_factory=RAM)

    def read(self, addr: int) -> int:
        if 0x0000 <= addr <= 0x1FFF:
            return self.ram.read(addr & 0x07FF)

        raise ValueError(f"Unsupported CPU bus read: {addr:04X}")

    def write(self, addr: int, value: int) -> None:
        if 0x0000 <= addr <= 0x1FFF:
            self.ram.write(addr & 0x07FF, value)
            return

        raise ValueError(f"Unsupported CPU bus write: {addr:04X}")

查看测试代码test_003_cpu_bus_to_ram.py

import pytest
from emulator.bus.cpu_bus import CpuBus
from emulator.memory.ram import RAM

def test_cpu_buss_class_exists():
    assert CpuBus is not None

def test_create_ram_instance():
    cpu_bus = CpuBus()

    assert isinstance(cpu_bus, CpuBus)

def test_cpu_bus_contains_ram_instance():
    cpu_bus = CpuBus()

    assert hasattr(cpu_bus, "ram")
    assert isinstance(cpu_bus.ram, RAM)


def test_cpu_bus_reads_and_writes_internal_ram():
    bus = CpuBus()
    bus.write(0x0000, 0x42)

    assert bus.read(0x0000) == 0x42
    
def test_cpu_bus_reads_and_writes_internal_ram_mirrors():
    bus = CpuBus()

    mirrors = [0x800, 0x1000, 0x1800]
    test_addresses = [0x0, 0x1, 0x42, 0x7FF]
    # Write different values in mirror address
    value = 0
    for base_address in mirrors:
        for address in test_addresses:
            bus.write(base_address + address, value & 0xFF)
            assert bus.read(address) == value & 0xFF
            value+=1
    
def test_cpu_bus_rejects_invalid_addresses():
    """Addresses should be unsigned 16 bits"""
    bus = CpuBus()

    invalid_addresses = [
        -1,
        0x10000,
        0x20000,
    ]

    for addr in invalid_addresses:
        with pytest.raises(ValueError):
            bus.write(addr, 0x42)


def test_cpu_bus_rejects_invalid_values():
    """Values should be unsigned 8 bits"""
    bus = CpuBus()

    invalid_values = [
        -1,
        0x100,
        0xFFFF,
    ]

    for value in invalid_values:
        with pytest.raises(ValueError):
            bus.write(0x0000, value)

测试函数 (7)

test_cpu_buss_class_exists
test_create_ram_instance
test_cpu_bus_contains_ram_instance
test_cpu_bus_reads_and_writes_internal_ram
test_cpu_bus_reads_and_writes_internal_ram_mirrors
test_cpu_bus_rejects_invalid_addresses
test_cpu_bus_rejects_invalid_values